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ladder diagram/standard C program NPN transistor output ARM CortexTM M3 CPU
Description:
* CPU: ARM CortexTM M3 CPU.
* Digital Input: Transistor input, supporting source drain type.
* Digital Output: NPN transistor output.
* High-Speed Input: 2-way AB input/4-way separate high-speed counting.
Specification:
| Timer | 256 100ms timer x206(0.1~3276.7 seconds),10ms timer x46(0.01~327.67 seconds), 1ms timer x4(0.001~32.767 seconds) |
| Counter | 235 |
| High-speed Interrupt | X0-X5 rising and falling edge interruption, 3-way timing interruption |
| Program Execution Model | Cycling scanning |
| Execution Speed | 0.1us/1000AWL ON:5us/OFF:0.5us) |
| Programming Language | Ladder diagram/standard C program (both can be used) |
| PORT1/PORT2 | ||
| Pin1 | Rx-(B) (PORT2 RS485) |  |
| Pin2 | RxD (PORT1 RS232) | |
| Pin3 | TxD (PORT1 RS232) | |
| Pin4 | NA | |
| Pin5 | GND | |
| Pin6 | Rx+(A) (PORT2 RS485) | |
| Pin7 | NA | |
| Pin8 | NA | |
| Pin9 | NA | |